Since flat display devices represented by liquid crystal display devices, are thin, light-weight, and have low power consumption, they are widely used as display devices in all types of apparatus. Recently, in order to realize even thinner, lighter and lower cost devices, in comparison with conventional amorphous silicon thin film transistors, technology has been established in which a drive circuit is configured using a low temperature polysilicon thin film transistor with high electron mobility, and this drive circuit is formed integrally on a glass substrate.
Furthermore, high resolution requirements of liquid crystal display devices in recent years are increasing day by day. The fact that amounts of information displayed at one time are increasing due to increasing resolution contributes to increased added value of the liquid crystal display devices. Moreover, by having a display device handle bidirectional scanning, it is possible to change direction of image to be displayed, according to direction of the liquid crystal display device. Therefore, it is desired to realize a liquid crystal display device with high added value, having a high resolution display region and a bidirectional scanning circuit.
Technology for realizing this type of liquid crystal display device is disclosed in Patent Documents 1 and 2. FIG. 28 is a schematic diagram of a flat display device described in Patent Document 1. In FIG. 28, a scanning line drive circuit 102, a signal line drive circuit 103, and a plurality (m×n) of switching elements 110 are disposed on an array substrate 101, in the flat display device. Scanning lines G1˜Gn are lines for transferring output of the scanning line drive circuit 102, as control signals of the switching elements 110. Furthermore, signal lines S1˜Sm are lines for transferring output of the signal line drive circuit 103 to source-drain of the switching elements 110.
In the abovementioned liquid crystal display device, a bidirectional shift register is used in at least one of the scanning line drive circuit 102 and the signal line drive circuit 103 The bidirectional shift register is configured from a plurality of unit registers connected in series, and has a function of shifting in a forward direction or a reverse direction by a three-phase shift clock signal.
FIG. 29 is circuit diagram of a unit register constituting a bidirectional shift register described in Patent Document 1. In FIG. 29, the unit register is provided with clock terminals C1, C2, and C3, a forward direction pulse input terminal INP, reverse direction pulse input terminal INN, an output terminal OUT, and shift direction control signals P and N, and is constituted of transistors tr1˜tr17.
An output circuit is constituted of the transistor tr1 having a conductive path between the clock terminal C1 and the output terminal OUT, and the transistor tr2 having a conductive path between a power supply electrode VDD and the output terminal OUT.
Furthermore, a transistor tr3 having a conductive path between the forward direction pulse input terminal INP and a control electrode of the transistor tr1, a transistor tr4 having a conductive path between the reverse direction pulse input terminal INN and the control electrode of the transistor tr1, and a transistor tr5 having a conductive path between the power supply electrode VDD and a control electrode of the transistor tr2, are provided, and an input circuit is provided which, in a forward direction pulse shift, conducts between the transistor tr3 and the transistor tr1, and also conducts between the forward direction pulse input terminal INP and a control electrode of the transistor tr5, and in a reverse direction pulse shift, conducts between the transistor tr4 and the transistor tr1, and also conducts between the reverse direction pulse input terminal INN and the control electrode of the transistor tr5.
Furthermore, a transistor tr6 having a conductive path between the clock terminal C2 and a control electrode of the transistor tr2, a transistor tr7 having a conductive path between the clock terminal C3 and the control electrode of the transistor tr2, and a transistor tr8 having a conductive path between the power supply electrode VDD and the control electrode of the transistor tr1, are provided, and a reset circuit is provided which, in a forward direction pulse shift, conducts between control electrodes of the transistor tr6 and the transistor tr2 and a control electrode of the transistor tr8, and in a reverse direction pulse shift, conducts between control electrodes of the transistor tr7 and the transistor tr2 and the control electrode of the transistor tr8.
Furthermore, an inversion prevention circuit is included which prevents voltage level in the control electrode of the transistor tr2 from inverting, in cases in which a voltage level of a clock signal inputted to the clock terminal C1 in a state in which the transistor tr1 is ON and the transistor tr2 is OFF, is inverted.
Moreover, the input circuit includes a transistor tr11 having a conductive path between the transistor tr3 and the control electrode of the transistor tr1, a transistor tr12 having a conductive path between the transistor tr4 and the transistor tr1, a transistor tr13 having a conductive path between the forward direction pulse input terminal INP and the transistor tr5, and a transistor tr14 having a conductive path between the reverse direction pulse input terminal INN and the transistor tr5; and turns ON the transistor tr11 and the transistor tr13 in the forward direction pulse shift, and turns ON the transistor tr12 and the transistor tr14 in the reverse direction pulse shift.
Furthermore, the reset circuit includes a transistor tr15 having a conductive path between the transistor tr6, the transistor tr2, and the transistor tr8, and a transistor tr16 having a conductive path between the transistor tr7, the transistor tr2, and the transistor tr8; and turns ON the transistor tr15 in the forward direction pulse shift, and turns ON the transistor tr16 in the reverse direction pulse shift.
Moreover, the inversion prevention circuit includes a transistor tr9 having a conductive path between the power supply electrode VDD and the control electrode of the transistor tr2, and a conductive path to the control electrode of the transistor tr1, and a transistor tr10 having a conductive path between the transistor tr9 and the transistor tr2, and a conductive path to the clock terminal C1.
According to the bidirectional shift register composed of this type of unit register, it is possible to prevent occurrence of variations in output signal, in the forward direction pulse shift and in the reverse direction pulse shift.
Next, a description will be given concerning a configuration of a bidirectional shift register disclosed in Patent Document 2. FIG. 30 is a block diagram of shift registers including cascade stages, in Patent Document 2. FIG. 30 has a configuration of a bidirectional scanning circuit in which outputs OUTn are arranged in a cascade. Each shift register stage 212 is driven by any of three-phase clock signals C1, C2, and C3, outputted from a clock generator 201. By switching the clock signals C1, C2, and C3, a shift direction of the shift register is controlled to be from bottom to top or from top to bottom.
FIG. 31 is a circuit diagram of a shift register stage (unit register) 212 used in the shift register of FIG. 30. The shift register stage 212 is provided with NMOS transistors 216, 217, 218, 218a, 219, 220, 220a, 221, 221a, 225, and 225a. 
In the NMOS transistor 216, a gate is connected to a node P1, a clock signal C1 (C3) is supplied to a drain, and a source is output OUTn. In the NMOS transistor 217, a gate is connected to a node P2, a drain is output OUTn, and a source is connected to a power supply VSSI. The NMOS transistors 216 and 217 form an output circuit and make active the output OUTn according to voltage level of the nodes P1 and P2.
Each of the NMOS transistors 218 and 218a are diode-connected, outputs OUTn−1 and OUTn+1 of adjacent shift register stages are connected to drains, and sources are commonly connected to the node P1. The NMOS transistors 218 and 218a form an input circuit from an adjacent shift register stage.
In the NMOS transistor 219, a gate is connected to the node P2, a drain is connected to the node P1, a source is connected to the power supply VSSI, and when the node P2 has a high level, the node P1 is at a low level.
In each of the NMOS transistors 220 and 220a, a drain is commonly connected to the power supply VDD, outputs OUTn+2 and OUTn−2 of shift register stages are connected to gates, and sources are commonly connected to the node P2. The NMOS transistors 220 and 220a are equivalent to a reset circuit.
In each of the NMOS transistors 221 and 221a, a drain is commonly connected to the node P2, outputs OUTn−1 and OUTn+1 of shift register stages are connected to gates, and sources are commonly connected to the power supply VSS. The NMOS transistors 221 and 221a form an input circuit from adjacent shift register stages.
In each of the NMOS transistors 225 and 225a, a drain is commonly connected to the node P1, outputs OUTn+2 and OUTn−2 of shift register stages are connected to gates, and sources are commonly connected to a power supply VDDI. The NMOS transistors 225 and 225a are equivalent to a reset circuit.
The shift register stage 212 configured as above outputs either of OUTn−1 and OUTn+1 of one adjacent shift register stage to another adjacent shift register stage from the output OUTn by the clock signal C1 (C3). In addition, output OUTn is put in a reset state by outputs OUTn+2 and OUTn−2 of two shift register stages away.
The shift register in which the shift register stages 212 are connected in series in this way does not require signals (P and N in FIG. 29) prescribing scanning direction, with regard to Patent Document 1, and realizes bidirectional scanning.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2004-185684A (FIG. 1 and FIG. 4)
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2001-506044A (FIG. 1 and FIG. 2)